AD9161BBCZ datasheet(97/144 Pages) AD

97 / 144 page

Data Sheet

AD9161/AD9162

Rev. D | Page 97 of 144

Hex.

Addr. Name

Bits Bit Name

Settings

Description

Reset

Access

0x095 DLL_FINE

[7:0] DLL_FINE

Fine delay line setpoint.

0x80

R/W

0x096 DLL_PHASE

[7:5] RESERVED

Reserved.

0x0

[4:0] DLL_PHS

Desired phase.

0x8

R/W

0 Minimum allowed phase.

16 Maximum allowed phase.

0x097 DLL_BW

[7:5] RESERVED

Reserved.

0x0

[4:2] DLL_FILT_BW

Phase measurement filter

bandwidth.

0x0

R/W

[1:0] DLL_WEIGHT

Tracking speed.

0x0

R/W

0x098 DLL_READ

[7:1] RESERVED

Reserved.

0x0

DLL_READ

Read request: 0 to 1 transition

updates the coarse, fine, and

phase readback values.

0x0

R/W

0x099 DLL_COARSE_RB

[7:6] RESERVED

Reserved.

0x0

[5:0] DLL_COARSE_RB

Coarse delay line readback.

0x0

0x09A DLL_FINE_RB

[7:0] DLL_FINE_RB

Fine delay line readback.

0x0

0x09B DLL_PHASE_RB

[7:5] RESERVED

Reserved.

0x0

[4:0] DLL_PHS_RB

Phase readback.

0x0

0x09D DIG_CLK_INVERT

[7:3] RESERVED

Reserved.

0x0

INV_DIG_CLK

Invert digital clock from DLL.

0x0

R/W

0 Normal polarity.

1 Inverted polarity.

DIG_CLK_DC_EN

Digital clock duty cycle

correction enable.

0x1

R/W

DIG_CLK_XC_EN

Digital clock cross control

enable.

0x1

R/W

0x0A0 DLL_CLK_DEBUG

DLL_TEST_EN

DLL clock output test enable.

0x0

R/W

[6:2] RESERVED

Reserved.

0x0

[1:0] DLL_TEST_DIV

DLL clock output divide.

0x0

R/W

0x110 INTERP_MODE

[7:4] JESD_LANES

Number of JESD204B lanes. For

proper operation of the

JESD204B data link, this signal

must only be programmed

while the QBD is held in soft

reset (Register 0x475, Bit 3), and

must not be changed during

normal operation.

0x8

R/W

[3:0] INTERP_MODE

Interpolation mode. For proper

operation of the JESD204B data

link, this signal must only be

programmed while the QBD is

held in soft reset (Register

0x475, Bit 3), and must not be

changed during normal

operation.

0x1

R/W

0000 1× (bypass) (this mode is not

supported in the

AD9161).

0001 2×.

0010 3×.

0011 4×.

0100 6×.

0101 8×.

0110 12×.

0111 16×.

1000 24×.

0x111 DATAPATH_CFG

INVSINC_EN

Inverse sinc filter enable.

0x0

R/W

0 Disable inverse sinc filter.

1 Enable inverse sinc filter.

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