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PCF8545 bảng dữ liệu(PDF) 14 Page - NXP Semiconductors |
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PCF8545 bảng dữ liệu(HTML) 14 Page - NXP Semiconductors |
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14 / 68 page ![]() NXP Semiconductors PCF8545 Universal LCD driver for multiplex rates up to 1:8 When the internal clock is used, or an external clock with EFR = 1, the LCD frame frequency can be programmed by software in steps of approximately 10 Hz in the range of 60 Hz to 300 Hz (see Table 17). Furthermore the internal oscillator is factory calibrated, see Table 33. 7.1.5 Command: set-MUX-mode The multiplex drive mode is configured with the bits described in Table 14. Bit Symbol Value Description 7 to 2 - 0000 00 fixed value 00[1], 01 1:8 multiplex drive mode; eight backplanes 10 1:6 multiplex drive mode; 6 backplanes 1 to 0 M[1:0] 11 1:4 multiplex drive mode; 4 backplanes Table 14. Set-MUX-mode - set multiplex drive mode command bit description [1] Default value. 7.1.6 Command: set-bias-mode The set-bias-mode command allows setting the bias level. Bit Symbol Value Description 7 to 2 - 0000 01 fixed value 00[1]. 01 1⁄4 bias 11 1⁄3 bias 1 to 0 B[1:0] 10 1⁄2 bias Table 15. Set-bias-mode - set bias mode command bit description [1] Default value. 7.1.7 Command: frame-frequency With the frame-frequency command, the frame frequency for the display can be configured. The clock frequency determines the frame frequency. Bit Symbol Value Description 7 to 5 - 001 fixed value 4 to 0 FD[4:0] see Table 17 frequency prescaler Table 16. Frame-frequency - frame frequency and output clock frequency command bit description When using an external clock it can be either a 230 kHz or a 9.6 kHz clock signal. The EFR bit (see Table 9) has to be set according to the external clock frequency. When EFR is set to 9.6 kHz, then the LCD frame frequency is calculated with Equation 1: (1) PCF8545 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 2 — 4 October 2021 14 / 68 |
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