Data Sheet

ADMV8526

REGISTER DETAILS

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Rev. 0 | 24 of 31

Address: 0x021, Reset: 0x00, Name: WR_BW

Table 24. Bit Descriptions for WR_BW

Bits

Bit Name

Description

Reset

Access

[7:0]

BW_LOAD_WR

Write Group: Bandwidth.

0x0

R/W

Address: 0x022, Reset: 0x00, Name: WR_MATCH

Table 25. Bit Descriptions for WR_MATCH

Bits

Bit Name

Description

Reset

Access

[7:0]

MATCH_LOAD_WR

Write Group: Match.

0x0

R/W

Address: 0x050, Reset: 0x00, Name: FILTER_CONFIG

Table 26. Bit Descriptions for FILTER_CONFIG

Bits

Bit Name

Description

Reset

Access

[7:1]

RESERVED

Reserved.

0x0

R

0

INTERPOLATE

Interpolation Enable. When this bit is set to 0, users must program the center frequency, bandwidth, and match.

When this bit is set to 1, the capacitors for the center frequency, bandwidth, and match are determined from

interpolation.

0x0

R/W

Address: 0x060, Reset: 0x00, Name: FC_READBACK

Table 27. Bit Descriptions for FC_READBACK

Bits

Bit Name

Description

Reset

Access

[7:0]

FC_READBACK

Center Frequency Read Back.

0x0

R