LMX9830 datasheet(13/46 Pages) NSC

13 / 46 page

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8.0 Functional Description

8.1 BASEBAND AND LINK MANAGEMENT

PROCESSORS

Baseband and Lower Link control functions are imple-

mented using a combination of National Semiconductor’s

CompactRISC 16-bit processor and the Bluetooth Lower

Link Controller. These processors operate from integrated

ROM memory and RAM and execute on-board firmware

implementing all Bluetooth functions.

8.1.1 Bluetooth Lower Link Controller

The integrated Bluetooth Lower Link Controller (LLC) com-

plies with the Bluetooth Specification version 2.0 and

implements the following functions:

■ Adaptive Frequency Hopping

■ Interlaced Scanning

■ Fast Connect

■ Support for 1, 3, and 5 slot packet types

■ 79 Channel hop frequency generation circuitry

■ Fast frequency hopping at 1600 hops per second

■ Power management control

■ Access code correlation and slot timing recovery

8.1.2 Bluetooth Upper Layer Stack

The integrated upper layer stack is prequalified and

includes the following protocol layers:

■ L2CAP

■ RFComm

■ SDP

8.1.3 Profile support

The on-chip application of the LMX9830 allows full stand-

alone operation, without any Bluetooth protocol layer nec-

essary outside the module. It supports the Generic Access

Profile (GAP), the Service Discovery Application Profile

(SDAP), and the Serial Port Profile (SPP).

The on-chip profiles can be used as interfaces to additional

profiles executed on the host. The LMX9830 includes a

configurable service database to answer requests with the

profiles supported.

8.1.4 Application with command interface

The module supports automatic slave operation eliminating

the need for an external control unit. The implemented

transparent option enables the chip to handle incoming

data raw, without the need for packaging in a special for-

mat. The device uses a pin to block unallowed connections.

This pincode can be fixed or dynamically set.

Acting as master, the application offers a simple but versa-

tile command interface for standard Bluetooth operation

like inquiry, service discovery, or serial port connection.

The firmware supports up to seven slaves. Default Link Pol-

icy settings and a specific master mode allow optimized

configuration for the application specific requirements. See

also Section "Integrated Firmware" on page 30.

8.1.5 Memory

The LMX9830 introduces 16 kB of combined system and

Patch RAM memory that can be used for data and/or code

upgrades of the ROM based firmware. Due to the flexible

startup used for the LMX9830 operating parameters like

the Bluetooth Device Address (BD_ADDR) are defined dur-

ing boot time. This allows reading out the parameters of an

external EEPROM or programming them directly over

UART.

8.1.6 External memory interfaces

As the LMX9830 is a ROM based device with no on-chip

non volatile storage, the operation parameters will be lost

after a power cycle or hardware reset. In order to prevent re

initializing such parameters, patches or even user data, the

LMX9830 offers two interfaces to connect an external

EEPROM to the device:

■ µ-wire/SPI

■ Access.bus (I2C compatible)

The selection of the interface is done during start up based

on the option pins. See Table 17 on page 17 for the option

pin descriptions.

8.1.7 µ-wire/SPI interface

In case the firmware is configured by the option pins to use

a µ-wire/SPI EEPROM, the LMX9830 will activate that inter-

face and try to read out data from the EEPROM. The exter-

nal memory needs to be compatible to the reference listed

in Table 10 on page 13. The largest size EEPROM support-

ed is limited by the addressing format of the selected NVM.

The device must have a page size equal to N x 32 bytes.

The firmware requires that the EEPROM supports Page

write. Clock must be HIGH when idle.

Table 10. M95640-S EEPROM 8Kx8

Parameter

Value

Supplier

ST Microelectronics

Supply Voltage1

Parameter range reduced to requirements of National

reference design

1.8 - 3.6V

Interface

SPI compatible (positive clock SPI

Modes)

Memory Size

8K x 8, 64kbit

Clock Rate1

2 MHz

Access

Byte and Page Write (up to

32bytes)

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