STM32F469AE datasheet(123/220 Pages) STMICROELECTRONICS

tên linh kiện	STM32F469AE

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DS11189 Rev 7

123/220

STM32F469xx

Electrical characteristics

191

5.3.12

PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic

interferences (see Table 54). It is available only on the main PLL.

Equation 1

The frequency modulation period (MODEPER) is given by the equation below:

fPLL_IN and fMod must be expressed in Hz.

As an example:

If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by

equation 1:

Equation 2

Equation 2 allows to calculate the increment step (INCSTEP):

fVCO_OUT must be expressed in MHz.

With a modulation depth (md) =

±2 % (4 % peak to peak), and PLLN = 240 (in MHz):

An amplitude quantization error may be generated because the linear modulation profile is

obtained by taking the quantized values (rounded to the nearest integer) of MODPER and

INCSTEP. As a result, the achieved modulation depth is quantized. The percentage

quantized modulation depth is given by the following formula:

As a result:

Table 44. SSCG parameters constraint

Symbol

Parameter

Min

Typ

Max(1)

1. Guaranteed by design.

Unit

fMod

Modulation frequency

KHz

Peak modulation depth

0.25

MODEPER * INCSTEP

215

− 1-

MODEPER

round fPLL_IN 4fMod









MODEPER

round 10

410









250

INCSTEP

round

–

 md PLLN



 100 5



MODEPER









INCSTEP

round

–

 2 240



 100 5



250









126md(quantitazed)%

mdquantized%

MODEPER INCSTEP



100





–

 PLLN







mdquantized%

250 126



100





–

 240







2.002%(peak)

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