PCF8536AT datasheet(7/48 Pages) NXP

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PCE85176AUG

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Product data sheet

Rev. 1 — 12 January 2015

7 of 48

NXP Semiconductors

PCE85176AUG

4 × 40 LCD segment driver for Chip-On-Glass

7.1.5 Command: blink-select

The blink-select command allows configuring the blink mode and the blink frequency.

[1]

Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.

[2]

Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.

7.2 Clock and frame frequency

7.2.1 Internal clock

The internal logic of the PCE85176AUG and its LCD drive signals are timed either by its

internal oscillator or by an external clock. The internal oscillator is enabled by connecting

pin OSC to pin VSS.

7.2.2 External clock

Pin CLK is enabled as an external clock input by connecting pin OSC to VDD.

Remark: A clock signal must always be supplied to the device; removing the clock may

freeze the LCD in a DC state, which is not suitable for the liquid crystal.

7.2.3 Timing

The PCE85176AUG timing controls the internal data flow of the device. This includes the

transfer of display data from the display RAM to the display segment outputs. The timing

also generates the LCD frame signal whose frequency is derived from the clock

frequency. The frame signal frequency is a fixed division of the clock frequency from either

the internal or an external clock:

Table 15.

Blink-select command bit allocation

Bit

Symbol

BF[1:0]

Table 16.

Blink-select command bit description

See Section 7.2.4.

Bit

Symbol

Value

Description

0, 1

see Table 6

6 to 3

1110

fixed value

2AB

blink mode selection

normal blinking[1]

alternate RAM bank blinking[2]

1 to 0

BF[1:0]

blink frequency selection (see Table 17)

off

clk

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