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PCF8536AT bảng dữ liệu(PDF) 14 Page - NXP Semiconductors |
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PCF8536AT bảng dữ liệu(HTML) 14 Page - NXP Semiconductors |
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14 / 54 page ![]() PCA8576F All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 3 December 2014 14 of 54 NXP Semiconductors PCA8576F Automotive 40 × 4 LCD driver The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCA8576F occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character. The hardware subaddress must not be changed while the device is being accessed on the I2C-bus interface. 7.3.7 Writing over the RAM address boundary In all multiplex drive modes, depending on the setting of the data pointer, it is possible to fill the RAM over the RAM address boundary. If the PCA8576F is part of a cascade the additional bits fall into the next device that also generates the acknowledge signal. If the PCA8576F is a single device or the last device in a cascade the additional bits will be discarded and no acknowledge signal will be generated. 7.3.8 Bank selection 7.3.8.1 RAM bank switching The PCA8576F includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. A bank can be thought of as one RAM row or a collection of RAM rows (see Figure 9). The RAM bank switching gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is complete. There are two banks; bank 0 and bank 1. Figure 9 shows the location of these banks relative to the RAM map. Input and output banks can be set independently from one another with the Bank-select command (see Table 10 on page 7). Figure 10 shows the concept. Fig 9. RAM banks in static and multiplex driving mode 1:2 |
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