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AS89010 bảng dữ liệu(PDF) 24 Page - ams AG |
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AS89010 bảng dữ liệu(HTML) 24 Page - ams AG |
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24 / 42 page ![]() ams.com db12348e_V3.11_preliminary_2017-07-06 Page 23 of 41 AS89010 V3.11 CREGH NAME VALUE [b] AFFECTED CONFIGURATION 11 synchronous measurement start and stop (SYND) 0023 divide by 2 01 divide by 4 10 divide by 8 11 divide by 16 023 disable digital divider 1 enable digital divider The measurement mode is controlled by the value of MODE. This assignment gives the opportunity to accommodate the current measurement to the given application (see chapter 5.1 for more details).The internally implemented divider which acts as digital downscaling of the converter gain can be set by the bits ENDIV and DIV. The bit SB controls the Standby operation of the device. In SYND Mode the bit ENTM enables the access to OUTINT to get time counts for internal measurement of the integration time, which can be of special interest if this time has been externally controlled. The time is measured as the number of internal clock counts with a width of up to 20 bit. The result is stored in register OUTINT that can be accessed via I²C interface (refer to chapter 5.5 for more details). |
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