ASL1507SHN datasheet(13/56 Pages) NXP

13 / 56 page

NXP Semiconductors

ASL1507SHN; ASL2507SHN

Single-phase and two-phase boost converter with limp-home mode

ASL1507_ASL2507

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Product data sheet

Rev. 1 — 26 April 2018

13 / 56

Table 10. Gate driver enable (address 01h)

Bit

Symbol Description

Value

Function

7 to 2 reserved reserved

000000

reserved; should remain clear for future use

phase 2 is off

1[1]

EN_G2

phase 2 enabled

phase 2 is enabled

phase 1 is off

EN_G1

phase 1 enabled

phase 1 is enabled

[1]

For the ASL1507SHN, this bit is reserved.

8.2.5 Configuration of the boost converter frequencies

The operation frequency of the boost converters is set via several SPI registers. To

ensure a stable phase delay between the different phases, all timings are derived from

the same oscillator. An integer number downscales the internal oscillator frequency for

each regulation loop. The slower clock controls the off-time of a phase and the delay

from one phase of the regulation loop to the next internal phase. The number of phases

determinates finally when the phase is turned on again and so defines the operation

frequency of the boost converter.

aaa-017533

PHASE CONTROL GENERATOR

combined

reset

Ph0

PHASE

GATING

COUNTER

COUNTER (DIV N)

switching

frequency

phase delay and

phase off parameters

phase active

phase_gen_rst

rst_n

clk

config change

Ph1

Ph2

Ph3

slope comp clk

Figure 8. Phase control generator

Table 11. Clock divider for VO1 (address 09h)

Bit

Symbol

Description

Value

Function

00h

clock is not divided

...

clock is divided by CLKDIV1[7:0] + 1

7 to 0 CLKDIV1[7:0] clock divider for

output voltage 1

FFh

clock is divided by 256

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