9 Detailed Description

9.1 Overview

The UCD7100 is a member of the UCD7K family of digital control compatible drivers for applications utilizing

digital control techniques, or applications requiring fast local peak current limit protection.

The UCD7100 is a low-side ±4-A high-current MOSFET gate driver. The UCD7100 allows digital power

controllers such as the UCD9110 or UCD9501 to interface to the power stage in single-ended topologies. It

provides a cycle-by-cycle current limit function with programmable threshold and a digital output current limit

flag, which can be monitored by the host controller. With a fast 25-ns cycle-by-cycle current limit protection,

the driver can turn off the power stage in the unlikely event that the digital system cannot respond to a failure

situation in time.

9.2 Functional Block Diagram

2

7

4

3

5

6

3V3 Regulator

&

Reference

UVLO

12

14

11

1

10

9

8

PVDD

N/C

3V3

IN

AGND

CLF

ILIM

OUT

OUT

PGND

PGND

CS

+

13 PVDD

VDD

25 mV

SD

Q

Q

R

9.3 Feature Description

9.3.1 Input

The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2 MHz. There is

an internal Schmitt Trigger comparator which isolates the internal circuitry from any external noise.

If limiting the rise or fall times to the power device is desired, then an external resistance can be added between

the output of the driver and the load device, which is generally a power MOSFET gate. The external resistor may

also help remove power dissipation from the package.

9.3.2 Current Sensing and Protection

A very fast current limit comparator connected to the CS pin is used to protect the power stage by implementing

cycle-by-cycle current limiting.

The current limit threshold is equal to the lesser of the positive inputs at the current limit comparator. The current

limit threshold can be set to any value between 0.25 V and 1.0 V by applying the desired threshold voltage to the

current limit (ILIM) pin. When the CS level is greater than the ILIM voltage minus 25 mV, the output of the driver

is forced low and the current limit flag (CLF) is set high. The CLF signal is latched high until the UCD7K device

receives the next rising edge on the IN pin.

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UCD7100

SLUS651E – MARCH 2005 – REVISED NOVEMBER 2021

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