S12SCIV2 datasheet(75/124 Pages) MOTOROLA

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MC9S12DT128B Device User Guide — V01.07

Section 6 HCS12 Core Block Description

Consult the HCS12 Core User Guide for information about the HCS12 core modules, i.e. central

processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed

external bus interface (MEBI), breakpoint module (BKP) and background debug mode module (BDM).

Section 7 Clock and Reset Generator (CRG) Block

Description

Consult the CRG Block User Guide for information about the Clock and Reset Generator module.

7.1 Device-specific information

7.1.1 XCLKS

The XCLKS input signal is active low (see 2.3.12 PE7 / NOACC / XCLKS — Port E I/O Pin 7).

Section 8 Enhanced Capture Timer (ECT) Block

Description

Consult the ECT_16B8C Block User Guide for information about the Enhanced Capture Timer

module.When the ECT_16B8C Block User Guide refers to freeze mode this is equivalent to active BDM

mode.

Section 9 Analog to Digital Converter (ATD) Block

Description

There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12DT128B.

Consult the ATD_10B8C Block User Guide for information about each Analog to Digital Converter

module. When the ATD_10B8C Block User Guide refers to freeze mode this is equivalent to active BDM

mode.

Section 10 Inter-IC Bus (IIC) Block Description

Consult the IIC Block User Guide for information about the Inter-IC Bus module.

Section 11 Serial Communications Interface (SCI) Block

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