EM78451AP datasheet(13/54 Pages) EMC

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EM78451

8-Bit Microcontroller

Product Specification (V1.2) 05.27.2004

• 9

(This specification is subject to change without further notice)

CES (bit 7): Clock Edge Select bit

1 = Data shifts out on falling edge, and shifts in on rising edge. Data is on hold during

high level.

0 = Data shifts out on rising edge, and shifts in on falling edge. Data is on hold during

low level.

SPIE (bit 6): SPI Enable bit

1= Enable SPI mode

0= Disable SPI mode

SRO (bit 5): SPI Read Overflow bit

1 = A new data is received while the previous data is still being held in the SPIB

this bit, users are required to read the SPIRB registers although only the transmission

has been implemented.

0 = No overflow.

NOTE

This can only occur in slave mode.

SSE (bit 4): SPI Shift Enable bit

1 = Start to shift, and keep on 1 while the current byte is still being transmitted.

0 = Reset as soon as the shifting is complete, and the next byte is ready to shift.

NOTE

This bit will reset to 0 at every one-byte transmission by the hardware

SBRS (bit 2~bit 0): SPI Baud Rate Select bits

SPI baud rate table is illustrated in the SPI section of this specification.

4.1.12 RE (TMR1: Timer1 register)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0X0E

TMR1/RE

TMR17 TMR16

TMR15

TMR14

TMR13

TMR12

TMR11 TMR10

TMR17~TMR10 is bit sets of timer1 register and it increases until the value matches

PWP and then it resets to 0.

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