EM78451AP datasheet(9/54 Pages) EMC

9 / 54 page

EM78451

8-Bit Microcontroller

Product Specification (V1.2) 05.27.2004

• 5

(This specification is subject to change without further notice)

In the case of EM78451, the most significant bit (A10,A11) will be loaded with the

content of bit PS0 ~PS1 in the status register (R3) upon the execution of a "JMP",

"CALL", or any other instructions which writes to R2.

All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instruction

that would change the contents of R2. Such instruction will need one more

instruction cycle.

A11A10

A9A8

CALL

RET

RETL

RETI

Stack 1

Stack 2

Stack 3

Stack 4

Stack 5

000

3FF

Page 0

400

7FF

Page 1

800

BFF

Page 2

C00

FFF

Page 3

001:Hareware interrupt location

002:Software interrupt (INT instruction) location

FFF:Reset location

Fig. 3 Program counter organization

4.1.4 R3 (Status Register)

PS1

PS0

Bit 0 (C) Carry flag

Bit 1 (DC) Auxiliary carry flag

Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.

Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset

to 0 by a "SLEP" command.

Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and the "WDTC" commands, or during

power up and reset to 0 with WDT timeout.

Bits 5 (PS0) ~ 6 (PS1) Page select bits. PS0~PS1 are used to pre-select a program

memory page. When executing a "JMP", "CALL", or other instructions which

causes the program counter to be changed (e.g. MOV R2, A), PS0~PS1 are

loaded into the 11th and 12th bits of the program counter where it selects one

of the available program memory pages. Note that RET (RETL, RETI)

instruction does not change the PS0~PS1 bits. That is, the return will always

be the page from where the subroutine was called, regardless of the current

settings of PS0~PS1 bits. PS1 bit is not used (read as "0") and cannot be

modified in EM78451.

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