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STM32H750VB bảng dữ liệu(PDF) 289 Page - STMicroelectronics

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STM32H750VB bảng dữ liệu(HTML) 289 Page - STMicroelectronics

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DS12556 Rev 5
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
311
7.3.29
Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 197 for DCMI are derived from
tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 120: General operating conditions, with the following configuration:
DCMI_PIXCLK polarity: falling
DCMI_VSYNC and DCMI_HSYNC polarity: high
Data formats: 14 bits
Capacitive load CL=30 pF
Measurement points are done at CMOS levels: 0.5VDD
VOS level set to VOS1
Figure 94. DCMI timing diagram
Table 197. DCMI characteristics(1)
Symbol
Parameter
Min
Max
Unit
-
Frequency ratio DCMI_PIXCLK/fHCLK
-0.4
-
DCMI_PIXCLK
Pixel Clock input
-
80
MHz
Dpixel
Pixel Clock input duty cycle
30
70
%
tsu(DATA)
Data input setup time
3
-
-
th(DATA)
Data hold time
1
-
tsu(HSYNC),
tsu(VSYNC)
DCMI_HSYNC/ DCMI_VSYNC input setup time
2
-
ns
th(HSYNC),
th(VSYNC)
DCMI_HSYNC/ DCMI_VSYNC input hold time
1
-
-
1. Guaranteed by characterization results.
MS32414V2
DCMI_PIXCLK
tsu(VSYNC)
tsu(HSYNC)
DCMI_HSYNC
DCMI_VSYNC
DATA[0:13]
1/DCMI_PIXCLK
th(HSYNC)
th(HSYNC)
tsu(DATA) th(DATA)



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