STM32H750VB datasheet(265/335 Pages) STMICROELECTRONICS

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DS12556 Rev 5

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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB

Electrical characteristics (rev V)

311

7.3.18

Quad-SPI interface characteristics

Unless otherwise specified, the parameters given in Table 179 and Table 180 for QUADSPI

are derived from tests performed under the ambient temperature, fAHB frequency and VDD

supply voltage conditions summarized in Table 120: General operating conditions, with the

following configuration:



Output speed is set to OSPEEDRy[1:0] = 11



Measurement points are done at CMOS levels: 0.5VDD



IO Compensation cell activated.



HSLV activated when VDD ≤ 2.7 V



VOS level set to VOS1

Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate

function characteristics.

The following table summarizes the parameters measured in SDR mode.

Table 178. LPSDR SDRAM Write timings(1)

1. Guaranteed by characterization results.

Symbol

Parameter

Min

Max

Unit

tw(SDCLK)

FMC_SDCLK period

2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5

td(SDCLKL _Data)

Data output valid time

2.5

th(SDCLKL _Data)

Data output hold time

td(SDCLKL_Add)

Address valid time

2.5

td(SDCLKL-SDNWE)

SDNWE valid time

2.5

th(SDCLKL-SDNWE)

SDNWE hold time

td(SDCLKL- SDNE)

Chip select valid time

th(SDCLKL- SDNE)

Chip select hold time

td(SDCLKL-SDNRAS)

SDNRAS valid time

1.5

th(SDCLKL-SDNRAS)

SDNRAS hold time

td(SDCLKL-SDNCAS)

SDNCAS valid time

1.5

td(SDCLKL-SDNCAS)

SDNCAS hold time

Table 179. QUADSPI characteristics in SDR mode(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Fck11/TCK

QUADSPI clock

frequency

2.7<VDD<3.6 V

CL = 20 pF

133

MHz

1.62<VDD<3.6 V

CL = 15 pF

100

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