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STM32H750VB bảng dữ liệu(PDF) 159 Page - STMicroelectronics |
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STM32H750VB bảng dữ liệu(HTML) 159 Page - STMicroelectronics |
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159 / 335 page ![]() DS12556 Rev 5 159/334 STM32H750VB STM32H750ZB STM32H750IB STM32H750XB Electrical characteristics (rev Y) 311 6.3.19 Delay block (DLYB) characteristics Unless otherwise specified, the parameters given in Table 85 for the delay block are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 22: General operating conditions. 6.3.20 16-bit ADC characteristics Unless otherwise specified, the parameters given in Table 85 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 22: General operating conditions. Table 84. Dynamics characteristics: Delay Block characteristics(1) 1. Guaranteed by characterization results. Symbol Parameter Conditions Min Typ Max Unit tinit Initial delay - 1400 2200 2400 ps t∆ Unit Delay - 35 40 45 Table 85. ADC characteristics(1) Symbol Parameter Conditions Min Typ Max Unit VDDA Analog power supply - 1.62 - 3.6 V VREF+ Positive reference voltage VDDA ≥ 2 V 2 - VDDA VDDA< 2 V VDDA VREF- Negative reference voltage - VSSA fADC ADC clock frequency 2 V≤VDDA≤3.3 V BOOST = 1 - - 36 MHz BOOST = 0 - - 20 fS Sampling rate for Fast channels, BOOST = 1, fADC = 36 MHz(2) 16-bit resolution - - 3.60(2) MSPS 14-bit resolution - - 4.00(2) 12-bit resolution - - 4.50(2) 10-bit resolution - - 5.00(2) 8-bit resolution 6.00(2) Sampling rate for Fast channels, BOOST = 0, fADC = 20 MHz 16-bit resolution - - 2.00(2) 14-bit resolution - - 2.20(2) 12-bit resolution - - 2.50(2) 10-bit resolution - - 2.80(2) 8-bit resolution 3.30(2) Sampling rate for Slow channels, BOOST = 0, fADC = 10 MHz 16-bit resolution - - 1.00 14-bit resolution - - 1.00 12-bit resolution - - 1.00 10-bit resolution - - 1.00 8-bit resolution 1.00 |
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