AS3977 datasheet(16/47 Pages) AMSCO

16 / 47 page

www.austriamicrosystems.com/AS3977

Revision 3.6

16 - 47

AS3977

Data Sheet - Ti m i n g C h a r a c t e r i s t i c s

7.1 Timing Parameters

Table 18. Timing Parameters

Symbol

Parameter

Condition

Min

Typ

Max

Units

General

BRSDI

Bit rate

Mbps

tCH

Clock high time

250

tCL

Clock low time

250

Write timing

tDIS

Data in setup time

tDIH

Data in hold time

tEH

Enable hold time

Read timing

tDIHZ

Data in to high impedance delay

time for the µC to release the DATAIO bus

tDOS

Data out setup time

130

tDOH

Data out hold time

135

tDOD

Data out delay

tDOHZ

Data out to high impedance delay

time for the SDI to release the DATAIO

bus

Timing parameters when leaving the Power Down Mode (for determination of CLK polarity and MCCLK behavior)

tCS

Clock setup time

(CLK polarity)

Setup time of CLK with respect to

ENABLE rising edge

tCHD

Clock hold time

(CLK polarity)

Hold time of CLK with respect to ENABLE

rising edge

tMS

Data in setup time

(MCCLK behavior)

DATAIO setup time with respect to

ENABLE rising edge

tMH

Data in hold time

(MCCLK behavior)

DATAIO hold time with respect to

ENABLE rising edge

AS3977 bảng dữ liệu(PDF) 16 Page - ams AG

AS3977 bảng dữ liệu(HTML) 16 Page - ams AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

bảng dữ liệu tải về

Link URL