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AS3956 bảng dữ liệu(PDF) 42 Page - ams AG

tên linh kiện AS3956
Giải thích chi tiết về linh kiện  NFC Forum Compliant Dynamic Tag
PDF  107 Pages
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nhà sản xuất  AMSCO [ams AG]
Trang chủ  http://www.ams.com
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AS3956 bảng dữ liệu(HTML) 42 Page - ams AG

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Page 42
ams Datasheet
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[v1-11] 2018-Nov-14
AS3956 − Detailed Description
Note(s):
1. This byte can always be accessed for read and write via SPI / I²C and can be accessed for read and write from the RF side if rfcfg_en
is set to 1. Bits tun_mod and ext_mod represents a default value stored in a volatile memory which can be modified after initialization
over SPI / I²C.
Bit rfcfg_en enables the personalization process during
production at customer facilities. When this bit is set to 0, the
modification of the last two blocks is not possible anymore over
the RF field.
If auth_set is set then changing of authenticated setting
(authentication limits, read/write permission) is enabled over
the RF after successful authentication. Password can always be
changed via the RF side if tag is in authenticated state
regardless of the value of read/write bits.
Bit nak_on_crc_parity configures error handling mechanism as
described in Error Handling.
Bit selr_b6_inv configures SEL_RES response on Cascade Level
2. If selr_b6_inv is set to 1, bit b6 in SEL_RES response on Cascade
Level 2 will be inverted, otherwise it will be set as configured
in SELR byte.
Bits powm<1:0> are setting power modes as defined in Power
Management.
Configuration Bytes MIRQ_0 and MIRQ_1
These two bytes define the default value of the volatile memory
for Mask Interrupt Register 0 and Mask Interrupt Register 1
registers. The default value for both bytes is 00h. These bytes
can always be accessed for read and write via the SPI / I²C and
can be accessed for read and write from the RF side if rfcfg_en
is set to 1.
b4
nak_on_crc_parity
0
1: Defines error handling and response
b3
auth_set
0
1: Configuration of the authentication
settings is enabled from RF side
b2
selr_b6_inv
0
1: Inverts bit 6 in SEL_RES response on
Cascade Level 2
b1
powm<1>
0
00: Power Mode 0
- Default Power
Mode
01: NA
10: NA
11: Power Mode 3-
External Supply
Used to Power
EEPROM and
Logic
b0
powm<0>
0
Conf. Bit
Name
Default
Function
Note



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