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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ADP1974ARUZ-R7 bảng dữ liệu(PDF) 10 Page - Analog Devices |
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ADP1974ARUZ-R7 bảng dữ liệu(HTML) 10 Page - Analog Devices |
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10 / 19 page  ADP1974 Data Sheet Rev. 0 | Page 10 of 19 THEORY OF OPERATION FREQ SYNC VIN VIN VBG = 1.252V SYNC DETECT 5µA VREG SS DISCHARGE COMP SS FAULT RS GND EN ADP1974 VREG AD8450 AD8450 DMAX SCFG TSD VREG UVLO BAND GAP MODE VREG DH DL DRIVE LOGIC OSCILLATOR CONFIG DETECT CL VREG EXTERNAL DRIVER 5V 15V 24V VOUT 500mV 450mV 300mV MODE SELECT 4V IFREQ ISS ICL 20µA IDT 20µA MODE SELECT PGND AGND 1MΩ 1MΩ 1MΩ 1kΩ IFREQ IFREQ RCL 20kΩ CIN 4.7µF CVREG 1µF COUT L M1 M2 RFREQ CSS RDMAX CDMAX VREG = 5V 8.5MΩ VREG VREG VREG 10µA RDT CDT DT 1.64pF VREG Figure 20. Internal Block Diagram The ADP1974 is a constant frequency, voltage mode, synchronous, PWM controller for bidirectional dc-to-dc applications. The ADP1974 is designed to be used with an external, high voltage FET half bridge driver, such as the ADuM7223, and an external error amplifier AFE device, such as the AD8450/AD8451, to implement a battery testing, charging, and discharging system. The ADP1974 has a high input voltage range, multiple externally programmed control pins, and integrated safety features. In buck mode, the device charges a battery and delivers energy from the input power source to the output. In boost mode, the device discharges a battery and delivers energy from the battery to the input. In both modes, the ADP1974 operates as a synchronous controller for maximum efficiency. SUPPLY PINS The ADP1974 has two voltage supply pins, VIN and VREG. The VIN pin operates from an external supply that ranges from 6 V to 60 V and is the supply voltage for the internal linear regulator of the ADP1974. Bypass the VIN pin to ground with a 4.7 μF or greater ceramic capacitor. The VREG pin is the output of the internal linear regulator. The internal regulator generates the 5 V (typical) rail that is used internally to bias the control circuitry and can be used externally as a pull-up voltage for the MODE, SYNC, DMAX, and FAULT pins. Bypass the VREG pin to ground with a 1 μF ceramic capacitor. VREG is disabled when EN is low and is active as long as VIN is above the internal UVLO (5.71 V typical) and EN is high. |
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