ADP1972ARUZ-R7 datasheet(15/18 Pages) AD

15 / 18 page

Data Sheet

ADP1972

Rev. B | Page 15 of 18

Selecting RFREQ for a Slave Device

To configure the ADP1972 as a slave device, drive VSCFG < 4.53 V.

When functioning as a slave device, the ADP1972 operates at

the frequency of the external clock applied to the SYNC pin. To

ensure proper synchronization, select RFREQ to set the frequency

to a value slightly slower than that of the master clock by using

the following equation:

RFREQ (SLAVE) = 1.11 × RFREQ (MASTER)

(5)

where:

RFREQ (MASTER) is the resistor value that corresponds to the

frequency of the master clock applied to the SYNC pin.

RFREQ (SLAVE) is the resistor value that appropriately scales the

frequency for the slave device, and 1.11 is the RFREQ slave to

master ratio for synchronization.

The frequency of the slave device is set to a frequency slightly

lower than that of the master device to allow the digital

synchronization loop of the ADP1972 to synchronize to the

master clock period. The slave device has approximately a 30%

range capability to adjust to match the master clock value.

Setting RFREQ (SLAVE) to 1.11× larger than RFREQ (MASTER) runs the

synchronization loop in approximately the center of the

adjustment range.

Programming the External Clock Phase Shift

If a phase shift is not required for slave devices, connect SCFG

of each slave device to ground. For devices that require a phase

shifted version of the synchronization clock that is applied to

the SYNC pin of the slave devices, connect a resistor (RSCFG)

from SCFG to ground to program the desired phase shift. To

determine the RSCFG for a desired phase shift (φSHIFT), start by

calculating the frequency of the slave clock (fSLAVE).

)

FREQ(SLAVE

SLAVE

(kHz) 

(6)

Next, calculate the period of the slave clock.



(kHz)

μs





SLAVE

(7)

where:

TSLAVE is the period of the master clock in μs.

fSLAVE is the frequency of the master clock in kHz.

Next, determine the phase time delay (TDELAY) for the desired

phase shift (φSHIFT) using the following equation:



 

360

μs

SLAVE

SHIFT

DELAY





(8)

where:

TDELAY is the phase delay in μs.

φSHIFT is the desired phase shift.

Lastly, to calculate the phase delay (TDELAY), use the following

equation:

RSCFG (kΩ) = 0.45 × RFREQ(SLAVE) (kΩ) + 50 × TDELAY (μs)

(9)

where:

RSCFG is the corresponding resistor for the desired phase shift

in kHz.

When using the phase shift feature, connect a capacitor of 47 pF

or greater in parallel with RSCFG.

Alternatively, the SCFG pin can be controlled with a voltage

source. When using an independent voltage source, ensure

VSCFG ≤ VREG under all conditions. When the ADP1972 is

disabled via the EN pin or UVLO, VREG = 0 V, and the voltage

source must adjust accordingly to ensure VSCFG ≤ VREG.

Figure 23 shows the internal voltage ramp of the ADP1972. The

voltage ramp has a well controlled 4 V p-p.

4.5V

0.5V

0.01T

0.99T

Figure 23. Internal Voltage Ramp

PROGRAMMING THE MAXIMUM DUTY CYCLE

The ADP1972 is designed with a 98% (typical) internal

maximum duty cycle. By connecting a resistor from DMAX to

ground, the maximum duty cycle can be programmed at any

value from 0% to 98%, using the following equation:









FREQ

DMAX

FREQ

MAX

(10)

where:

DMAX is the programmed maximum duty cycle.

VFREQ is 1.252 V (typical).

RDMAX is the value of the resistance used to program the

maximum duty cycle.

RFREQ is the frequency set resistor used in the application.

The current source of DMAX is equivalent to the programmed

current of the FREQ pin:

FREQ

DMAX



(11)

where IDMAX = IFREQ = the current programmed on the

FREQ pin.

The maximum allowable duty cycle of the ADP1972 is 98%

(typical). If the resistor on DMAX sets a maximum duty cycle

larger than 98%, the ADP1972 defaults to its internal

maximum. If the 98% internal maximum duty cycle is sufficient

for the application, tie the DMAX pin to VREG or leave it floating.

The CDMAX capacitor connected from the DMAX pin to GND

must be 47 pF or greater.

ADP1972ARUZ-R7 bảng dữ liệu(PDF) 15 Page - Analog Devices

ADP1972ARUZ-R7 bảng dữ liệu(HTML) 15 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

bảng dữ liệu tải về

Link URL