ADP1972ARUZ-R7 datasheet(12/18 Pages) AD

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ADP1972

Data Sheet

PWM DRIVE SIGNALS

The ADP1972 has two output drive signals, DH and DL, that

are compatible with drivers similar to the IR2110S.

The drive signal DL is active when the MODE pin is logic low

and the ADP1972 is configured in the boost/recycle mode. The

DL drive signal turns on and off the low-side switch driven from

the external driver. While in the boost/recycle mode, the DH

signal is driven low to prevent the high-side switch from turning

on and only allows the body diode to conduct.

The drive signal DH is active when the MODE pin is logic high

and the ADP1972 is configured in the buck/charge mode. The

DH drive signal turns on and off the high-side switch driven

from the external driver. While in the buck/charge mode, the

DL signal is driven low to prevent the low-side switch from

turning on, and it only allows the body diode to conduct.

When driving capacitive loads with the DH and DL pins, a

20 Ω resistor must be placed in series with the capacitive load

to reduce ground noise and ensure signal integrity.

EXTERNAL COMP CONTROL

The ADP1972 COMP pin is the input to the error amplifier that

controls the PWM output on the DH pin or DL pin. The ADP1972

uses voltage mode control that compares an error signal, applied to

the COMP pin by an external device, such as the AD8450, to an

internal 4 V p-p triangle waveform. As the load changes, the error

signal increases or decreases. The internal PWM comparator

determines the appropriate duty cycle drive signal by monitoring

the error signal at the COMP pin and the internal 4 V p-p ramp

signal. The internal PWM comparator subsequently drives the

external gate driver at the determined duty cycle through the DH

and DL drive control pins.

The functional voltage range of the COMP pin is from 0 V to

5.0 V. If VCOMP is less than 0.5 V (typical), the DH and DL

outputs are disabled. If VCOMP is between 0.5 V and 4.5 V, the

ADP1972 regulates the DH and DL outputs accordingly. If

VCOMP is greater than 4.5 V, the ADP1972 operates the DH and

DL outputs at the maximum programmed duty cycle (98%

default). The input to the COMP pin must never exceed the

5.5 V absolute maximum rating.

The DL and DH signals swing from VREG (5 V typical) to ground.

The external FET driver used must have input control pins

compatible with a 5 V logic signal.

CURRENT LIMIT

The ADP1972 features a peak hiccup current limit implementation.

When the peak inductor current exceeds the programmed current

limit for more than 500 consecutive clock cycles, 5.2 ms (typical)

for a 100 kHz programmed frequency, the peak hiccup current

limit condition occurs. PWM regulation of the output voltage

then disables for 500 clock cycles, which is enough time for the

output to discharge, and the average power dissipation to reduce.

When the 500 clock cycles have expired, the ADP1972 restarts.

When the SS pin exceeds 0.52 V (typical), the ADP1972 resumes

PWM regulation.

Figure 21 shows the current limit block diagram for peak

current limit protection.

VREG

500mV

300mV

ICL

20µA

RCL

20kΩ

MODE

SELECT

Figure 21. Current Limit Block Diagram

PWM FREQUENCY CONTROL

The FREQ, SYNC, and SCFG pins are all used to determine the

source, frequency, and synchronization of the clock signal that

operates the PWM control of the ADP1972.

Internal Frequency Control

The ADP1972 frequency can be programmed with an external

resistor connected between FREQ and ground. The range of

frequency can be set from a minimum of 50 kHz to a maximum

of 300 kHz. If the SCFG pin is tied to VREG, forcing VSCFG ≥ 4.53 V,

or if the SCFG pin is left floating, the SYNC pin is configured as

an output, and the ADP1972 operates at the frequency set by

RFREQ, which outputs from the SYNC pin through the open drain

device. The output clock of the SYNC pin operates with a 50%

(typical) duty cycle. In this configuration, the SYNC pin can be

used to synchronize other switching regulators in the system to

the ADP1972. When the SYNC pin is configured as an output,

an external pull-up resistor is needed from the SYNC pin to an

external supply. The VREG pin of the ADP1972 is used as the

external supply rail for the pull-up resistor.

External Frequency Control

When VSCFG ≤ 0.5 V, the SYNC pin is configured as an input,

and the ADP1972 synchronizes to the external clock applied to

the SYNC pin and operates as a slave device. This synchronization

allows the ADP1972 to operate at the same switching frequency

with the same phase as other switching regulators or devices in

the system. When operating the ADP1972 with an external

clock, select RFREQ to provide a frequency that approximates but

is not equal to the external clock frequency, which is further

explained in the Applications Information section.

Operating Frequency Phase Shift

When the voltage applied to the SCFG pin is 0.65 V < VSCFG <

4.25 V, the SYNC pin is configured as an input, and the ADP1972

synchronizes to a phase shifted version of the external clock

applied to the SYNC pin. To adjust the phase shift, place a

resistor (RSCFG) from SCFG to ground. The phase shift reduces

the input supply ripple for systems containing multiple

switching power supplies.

Rev. B | Page 12 of 18

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