ADP1052ACPZ-R7 datasheet(94/113 Pages) AD

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ADP1052

Data Sheet

Rev. B | Page 94 of 113

DIGITAL COMPENSATOR AND MODULATION

SETTING REGISTERS

POLE LOCATION

RANGE

ZERO

100Hz

500Hz

1kHz

5kHz

10kHz

POLE

LF FILTER

HF FILTER

Figure 66. Digital Compensator Programmability

Table 147. Register 0xFE30—Normal Mode Compensator

Low Frequency Gain Settings

Bits

Bit Name/

Function

R/W

Description

[7:0]

Normal mode

low frequency

gain

R/W

This register determines the low

frequency gain of the digital

compensator in normal mode. It is

programmable over a 48.13 dB

range. See Figure 66.

Table 148. Register 0xFE31—Normal Mode Compensator

Zero Settings

Bits

Bit Name/

Function

R/W

Description

[7:0]

Normal

mode

zero settings

R/W

This register determines the position

of the zero of the digital compensator

in normal mode. See Figure 66.

Table 149. Register 0xFE32—Normal Mode Compensator

Pole Settings

Bits

Bit Name/

Function

R/W

Description

[7:0]

Normal

mode

pole settings

R/W

This register determines the position

of the pole of the digital compensator

in normal mode. See Figure 66.

Table 150. Register 0xFE33—Normal Mode Compensator

High Frequency Gain Settings

Bits

Bit Name/

Function

R/W

Description

[7:0]

Normal mode

high

frequency

gain

R/W

This register determines the high

frequency gain of the digital

compensator in normal mode. It is

programmable over a 48.13 dB

range. See Figure 66.

Table 151. Register 0xFE34—Light Load Mode Compensator

Low Frequency Gain Settings

Bits

Bit Name/

Function

R/W

Description

[7:0]

Light load

mode low

frequency

gain

R/W

This register determines the low frequency

gain of the digital compensator in light

load mode and deep light load mode. It is

programmable over a 48.13 dB range. See

Figure 66.

Table 152. Register 0xFE35—Light Load Mode Compensator

Zero Settings

Bits

Bit Name/

Function

R/W

Description

[7:0]

Light load

mode zero

setting

R/W

This register determines the position

of the zero of the digital

compensator in light load mode and

deep light load mode. See Figure 66.

Table 153. Register 0xFE36—Light Load Mode Compensator

Pole Settings

Bits

Bit Name/

Function

R/W

Description

[7:0]

Light load

mode pole

setting

R/W

This register determines the

position of the pole of the digital

compensator in light load mode and

deep light load mode. See Figure 66.

Table 154. Register 0xFE37—Light Load Mode Compensator

High Frequency Gain Settings

Bits

Bit Name/

Function

R/W

Description

[7:0]

Light load mode

high frequency

gain

R/W

This register determines the

high frequency gain of the

digital compensator in light

load mode and deep light load

mode. It is programmable over a

48.13 dB range. See Figure 66.

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