DS1689SSLASHT&R datasheet(4/36 Pages) MAXIM

4 / 36 page

DS1689/DS1693

4 of 36

EDIP

NAME

FUNCTION

SQW

Square-Wave Output. The SQW pin can output a signal from one of

13 taps provided by the 15 internal divider stages of the real time

clock. The frequency of the SQW pin can be changed by

programming Register A as shown in Table 2. The SQW signal can

be turned on and off using the SQWE bit in Register B. A 32kHz

SQW signal is output when SQWE = 1, the Enable 32kHz (E32K)

bit in extended register 04BH is logic 1, and VCC is above VPF. A

32kHz square wave is also available when VCC is less than VPF if

E32K = 1, ABE = 1, and voltage is applied to VBAUX.

VCCO

External SRAM Power-Supply Output. This pin is internally

connected to VCCI when VCCI is within nominal limits. However,

during power fail, VCCO is internally connected to the VBAT or VBAUX

(whichever is larger). For 5V operation, switchover from VCCI to the

backup supply occurs when VCCI drops below the larger of VBAT and

VBAUX. For 3V operation, switchover from VCCI to the backup supply

occurs at VPF if VPF is less than VBAT and VBAUX. If VPF is greater

than VBAT and VBAUX, the switch from VCCI to the backup supply

occurs when VCCI drops below the larger of VBAT and VBAUX.

VCCI

+3V or +5V Main Supply. DC power is provided to the device on

these pins. 5V operation is selected when the PSEL pin is at logic 1.

If PSEL is floated or at logic 0, the device is in autosense mode and

determines the correct operating voltage based on the VCCI voltage

level.

CEO

Active-Low RAM Chip Enable Output. When power is valid,

CEO

will equal

CEI. When power is not valid, CEO will be driven high

regardless of

CEI.

CEI

Active-Low RAM Chip Enable Input.

CEI should be driven low to

enable the external RAM.

—

2, 3,

19, 23

N.C.

No Connection

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