SH7041A datasheet(647/923 Pages) RENESAS

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18.3.2

Port A I/O Register L (PAIORL)

The port A I/O register L (PAIORL) is a 16-bit read/write register that selects input or output for

the least significant 16 pins of port A. Bits PA15IOR–PA0IOR correspond to pins PA15/CK–

PA0/RXD0. PAIORL is enabled when the port A pins function as general input/outputs (PA15–

PA0), or with the serial clock (SCK1, SCK0). For other functions, it is disabled.

When the port A pin functions PA15–PA0 are SCK1, SCK0, a given pin in port A is an output pin

if its corresponding PAIORL bit is set to 1, and an input pin if the bit is cleared to 0.

PAIORL is initialized to H'0000 by external power-on reset; however, it is not initialized for

manual resets, reset by WDT, standby mode, or sleep mode, so the previous data is maintained.

Bit:

PA15

IOR

PA14

IOR

PA13

IOR

PA12

IOR

PA11

IOR

PA10

IOR

PA9

IOR

PA8

IOR

Initial value:

R/W:

R/W

Bit:

PA7

IOR

PA6

IOR

PA5

IOR

PA4

IOR

PA3

IOR

PA2

IOR

PA1

IOR

PA0

IOR

Initial value:

R/W:

R/W

18.3.3

Port A Control Register H (PACRH)

PACRH is a 16-bit read/write register that selects the multiplex pin function for the eight most

significant pins of port A. PACRH selects the PA23/

WRHH–PA16/AH pin functions.

The eight most significant pins of port A have bus control signals (

WRHH, WRHL, CASHH,

CASHL, BACK, BREQ, WAIT, AH) and DMAC control signals (DRAK1, DRAK0), but there

are instances when the register settings that select these pin functions will be ignored. Refer to

table 18.2, Pin Arrangement by Mode.

PACRH is initialized to H'0000 by external power-on reset but is not initialized for manual resets,

reset by WDT, standby mode, or sleep mode, so the previous data is maintained.

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