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SH7041A bảng dữ liệu(PDF) 631 Page - Renesas Technology Corp

tên linh kiện SH7041A
Giải thích chi tiết về linh kiện  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
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17.2.4
Compare Match Timer Constant Register (CMCOR)
The compare match timer constant register (CMCOR) is a 16-bit register that sets the compare
match period with the CMCNT.
The CMCOR is initialized to H'FFFF by power-on resets and by standby mode. There is no
initializing with manual reset.
Bit:
15
14
13
12
11
10
9
8
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
17.3
Operation
17.3.1
Period Count Operation
When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR
bit of the CMSTR is set to 1, the CMCNT begins incrementing with the selected clock. When the
CMCNT counter value matches that of the compare match constant register (CMCOR), the
CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is set to 1. If the
CMIE bit of the CMCSR register is set to 1 at this time, a compare match interrupt (CMI) is
requested. The CMCNT counter begins counting up again from H'0000.
Figure 17.2 shows the compare match counter operation.
CMCOR
H'0000
CMCNT value
Time
Counter cleared by
CMCOR compare match
Figure 17.2 Counter Operation



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