SH7041A datasheet(630/923 Pages) RENESAS

tên linh kiện	SH7041A

Giải thích chi tiết về linh kiện	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

Scroll/Zoom	100%

nhà sản xuất	RENESAS [Renesas Technology Corp]

Trang chủ	http://www.renesas.com

Logo

630 / 923 page

592

• Bits 1, 0—Clock Select 1, 0 (CKS1, CKS0): These bits select the clock input to the CMCNT

from among the four internal clocks obtained by dividing the system clock (

φ). When the STR

bit of the CMSTR is set to 1, the CMCNT begins incrementing with the clock selected by

CKS1 and CKS0.

Bit 1: CKS1

Bit 0: CKS0

Description

φ/8 (initial status)

φ/32

φ/128

φ/512

17.2.3

Compare Match Timer Counter (CMCNT)

The compare match timer counter (CMCNT) is a 16-bit register used as an upcounter for

generating interrupt requests.

When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR

bit of the CMSTR is set to 1, the CMCNT begins incrementing with that clock. When the CMCNT

value matches that of the compare match timer constant register (CMCOR), the CMCNT is

cleared to H'0000 and the CMF flag of the CMCSR is set to 1. If the CMIE bit of the CMCSR is

set to 1 at this time, a compare match interrupt (CMI) is requested.

The CMCNT is initialized to H'0000 by power-on resets and by standby mode. Manual reset does

not initialize CMCNT.

Bit:

Initial value:

R/W:

R/W

Bit:

Initial value:

R/W:

R/W

SH7041A bảng dữ liệu(PDF) 630 Page - Renesas Technology Corp