SH7041A datasheet(601/923 Pages) RENESAS

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When the DTC or DMAC are activated by an ADI interrupt, the ADF flag is cleared to 0 when the

final specified data register is read.

Table 15.9

High Speed A/D Converter Interrupt Sources

Interrupt Source

Description

DTC, DMAC Activation

ADI

Interrupt caused by conversion end

Possible

15.6

Notes on Use

Take note of the following for the A/D converter.

Analog input voltage range

During A/D conversions, see that the voltage applied to the analog input pins AN0–AN7 is

within the range Avss

≤ AN0–AN7 ≤ AVcc.

AVcc and AVss input voltages

The AVcc and AVss input voltage must be AVcc = Vcc ± 10%, AVss = Vss. When not using

the A/D converter, use AVcc = Vcc, AVss = Vss. During the standby mode, use V

RAM ≤ Avcc

≤ 5.5V, AVss = Vss. V

RAM is the RAM standby voltage.

AVref input voltage

The analog standard voltage AVref (AV

ref) must be Avref ≤ AVcc. When not using the A/D

converter, use AV

ref = Vcc. During the standby mode, use VRAM ≤ AVref ≤ AVcc. VRAM is the

RAM standby voltage.

Input ports

The time constant for the circuit connecting to the input port must be shorter than the sampling

time of the A/D converter. Input voltage may not be sampled sufficiently when the time

constant of the circuit is long.

Conversion start modes

Depending on the PWR bit setting, the demand for A/D conversion will differ for the high-

speed start mode and low-demand conversion mode.

Analog input pins handling

Connect a protection circuit as shown in figure 15.14 to prevent analog input pins (AN0–AN7)

from being destroyed due to abnormal voltage from surge, etc. This circuit is also equipped

with a CR filter to control errors due to noise. The circuit shown in the diagram is only an

example and the number of circuits is to be determined by considering the actual condition of

use.

Figure 15.15 shows an equivalent circuit of analog input pins and table 15.10 shows the

specification of the analog input pins.

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