SH7041A datasheet(593/923 Pages) RENESAS

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Table 15.5

Conversion Channel and ADF Flag Setting/Clearing Conditions During Buffer

Operation 2

Channel Setting

Sampling Channel

CH2 CH1 CH0

BUFE1, BUFE0 = B'01 BUFE1, BUFE0 = B'10 BUFE1, BUFE0 = B'11

00—

AN0, AN2 (ADDRC)

AN0, AN2, AN3

(ADDRD)

AN0, AN2–AN4

(ADDRE)

AN0, AN1, AN4

(ADDRE)

AN0, AN4 (ADDRE)

AN0, AN2–AN5

(ADDRF)

AN0, AN1, AN4, AN5

(ADDRF)

AN0, AN4, AN5

(ADDRF)

AN0, AN2–AN6

(ADDRG)

AN0, AN1, AN4–AN6

(ADDRG)

AN0, AN4–AN6

(ADDRG)

AN0, AN2–AN7

(ADDRH)

AN0, AN1, AN4–AN7

(ADDRH)

AN0, AN4–AN7

(ADDRH)

Note: * See table 15.4.

ADF Flag Clearing: When the DTC and DMAC are started up due to an A/D conversion end

interrupt, the ADF flag is cleared when the ADDR specified in table 15.4 or 15.5 has been read.

Resetting the Number of Buffer Operations: Clear the BUFE1 and BUFE0 bits to B'00 in

conversion standby mode or when the converter has been halted. The number of buffer operations

is cleared to 0.

Updating Buffer Operations: Clear the BUFE1 and BUFE0 bits to B'00 in conversion standby

mode or when the converter has been halted. Thereafter, set BUFE1 and BUFE0, and the buffer

operations shown in tables 15.4 and 15.5 are performed when conversion is resumed.

15.4.6

Simultaneous Sampling Operation

With simultaneous sampling, continuous conversion is conducted with sampling of the input

voltages on two channels at the same time. Simultaneous sampling is valid in group mode.

Channels for sampling are determined by the CH2 and CH1 bits of the RDSCR. The combinations

are shown in table 15.6. For example, if GRP = 1 when CH2 and CH1 = B'11, sampling occurs in

order in the following pairs: AN0, AN1

→AN2, AN3→AN4, AN5→AN6, AN7. Sampling timing

is shown in figure 15.9.

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