SH7041A datasheet(544/923 Pages) RENESAS

tên linh kiện	SH7041A

Giải thích chi tiết về linh kiện	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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506

Initialize

Clear TE and RE bits to 0 in SCR

Set CKE1 and CKE0 bits in SCR

(TE and RE bits are 0)

Select transmit/receive format in SMR

Set value to BRR

Wait

Set TE or RE to 1 in SCR; Set RIE,

TIE, TEIE, and MPIE as necessary

1-bit interval elapsed?

End

Yes

Figure 14.4 Sample Flowchart for SCI Initialization

Transmitting Serial Data (Asynchronous Mode): Figure 14.5 shows a sample flowchart for

transmitting serial data. The procedure is as follows (the steps correspond to the numbers in the

flowchart):

1.SCI initialization: Set the TxD pin using the PFC.

2.SCI status check and transmit data write: Read the serial status register (SSR), check that the

TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE

to 0.

3.Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it

reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC or the DTC is

started by a transmit-data-empty interrupt request (TxI) in order to write data in TDR, the

TDRE bit is checked and cleared automatically.

4.To output a break at the end of serial transmission, first clear the port data register (DR) to 0,

then clear the TE to 0 in SCR and use the PFC to establish the TxD pin as an output port.

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