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SH7041A bảng dữ liệu(PDF) 542 Page - Renesas Technology Corp

tên linh kiện SH7041A
Giải thích chi tiết về linh kiện  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
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SH7041A bảng dữ liệu(HTML) 542 Page - Renesas Technology Corp

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504
Transmit/Receive Formats: Table 14.10 shows the 11 communication formats that can be
selected in the asynchronous mode. The format is selected by settings in the serial mode register
(SMR).
Table 14.10 Serial Communication Formats (Asynchronous Mode)
SMR Bits
Serial Transmit/Receive Format and Frame Length
CHR PE
MP
STOP
1
2
345678
9
10
11
12
0
0
0
0
START
8-Bit data
STOP
0
0
0
1
START
8-Bit data
STOP STOP
0
1
0
0
START
8-Bit data
P
STOP
0
1
0
1
START
8-Bit data
P
STOP STOP
1
0
0
0
START
7-Bit data
STOP
1
0
0
1
START
7-Bit data
STOP STOP
1
1
0
0
START
7-Bit data
P
STOP
1
1
0
1
START
7-Bit data
P
STOP STOP
0
—
1
0
START
8-Bit data
MPB
STOP
0
—
1
1
START
8-Bit data
MPB
STOP STOP
1
—
1
0
START
7-Bit data
MPB
STOP
1
—
1
1
START
7-Bit data
MPB
STOP STOP
—: Don’t care bits.
Note:
START: Start bit
STOP: Stop bit
P: Parity bit
MPB: Multiprocessor bit
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected
by the C/
A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control
register (SCR) (table 14.9).



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