SH7041A datasheet(409/923 Pages) RENESAS

tên linh kiện	SH7041A

Giải thích chi tiết về linh kiện	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

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• Complementary PWM mode 0% and 100% duty output

In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures

12.48 to 12.52 show output examples.

100% duty output is performed when the data register value is set to H'0000. The waveform in

this case has a positive phase with a 100% on-state. 0% duty output is performed when the data

phase with a 100% off-state.

On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn-

off compare-match for the same phase occur simultaneously, both compare-matches are

ignored and the waveform does not change.

• Toggle output synchronized with PWM cycle

In complementary PWM mode, toggle output can be performed in synchronization with the

PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR).

An example of a toggle output waveform is shown in figure 12.53.

This output is toggled by a compare-match between TCNT3 and TGR3A and a compare-match

between TCNT4 and H'0000.

The output pin for this toggle output is the TIOC3A pin. The initial output is 1.

TGR3A

H'0000

Toggle output

TIOC3A pin

TCNT4

TCNT3

Figure 12.53 Example of Toggle Output Waveform Synchronized with PWM Output

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