Z8932320FSC datasheet(28/60 Pages) ZILOG

28 / 60 page

Z89223/273/323/373

16-Bit Digital Signal Processors with A/D Converter

ZiLOG

DS000202-DSP0599

REGISTERS (Continued)

The following are not actually registers, but are read or writ-

ten in the same way as hardware registers on the chip:

BUS

is a read-only register which, when accessed, returns

the contents of the D-Bus. BUS is used for emulation only.

Dn:b

refers to locations in RAM that can be used as a pointer

to locations in program memory which is efficient for co-

efficient addressing. The programmer decides which loca-

tion to choose from two bits in the status register and two

bits in the operand. Thus, only the lower 16 possible loca-

tions in RAM can be specified. At any one time, there are

eight usable pointers, four per bank, and the four pointers

are in consecutive locations in RAM. For example, if

S3/S4=01 in the status register, then D0:0/D1:0/D2:0/D3:0

refer to register locations 4/5/6/7 in RAM Bank 0. Note that

when the data pointers are being written to, a number is ac-

tually being loaded to Data RAM, so they can be used as a

limited method for writing to RAM.

EXTn

are external registers (n = 0 to 6). These are seven

16-bit register addresses provided for mapping internal and

external peripherals into the address space of the processor.

Note that for external peripherals the actual register RAM

does not exist on the chip, but would exist as part of the ex-

ternal device, such as an A/D result latch. The External Ad-

dress Bus, EA2–EA0, the External Data Bus, ED15–ED0,

DS, WAIT, and RD/WR are used to access external periph-

erals.

EXT7

is used for Register Bank Select, and to program wait

states for EXT0–EXT6, and is not available for accessing

an external peripheral.

Table 12. RPL Description

Loop Size

256

128

BUS

D-Bus

Dn:b

Eight Data Pointers

EXTn

External Register, 16-bit

Figure 19. Status Register

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

256

128

"Short Form Direct" bits

User Output UO1, UO0

(Complemented)

Global Interrupt Enable

Overflow Protection

MPY output arithmetically

shifted right by three bits

User Input UI1,UI0

(Read Only)

Carry

Zero

Overflow

Negative

Ram

Pointer

Loop

Size

S15

S14

S13

S12

S11

S10

NOV

UI1

UI0

SH3

UO1 UO0

RPL

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