SST26VF040A-80ISLASHSNVAO datasheet(16/73 Pages) MICROCHIP

tên linh kiện	SST26VF040A-80I/SNVAO

Giải thích chi tiết về linh kiện	2.5V/3.0V 4-Mbit Serial Quad I/O??(SQI?? Flash Memory

PDF	73 Pages

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DS20006292B-page 16

SST26VF040A

FIGURE 5-1:

RESET SEQUENCE

5.3

Read (40 MHz)

The READ instruction, 03H, is supported in SPI bus

protocol only with clock frequencies up to 40 MHz.

This command is not supported in SQI bus protocol.

The device outputs the data starting from the specified

address location, then continuously streams the data

output through all addresses until terminated by a

low-to-high transition on CE#. The internal Address

Pointer will automatically increment until the highest

memory address is reached. Once the highest memory

address is reached, the Address Pointer will

automatically return to the beginning (wrap-around) of

the address space.

Initiate the READ instruction by executing an 8-bit

command, 03H, followed by address bits A[23:0].

CE# must remain active-low for the duration of the

Read cycle. See Figure 5-2 for the Read sequence.

FIGURE 5-2:

READ SEQUENCE (SPI)

Note: C[1:0] = 66H; C[3:2] = 99H

MODE 3

CLK

SIO[3:0]

CE#

MODE 3

C3 C2

MODE 0

MODE 3

MODE 0

TCPH

CE#

SCK

ADD.

0 1 234 5 6 78

ADD.

High-Impedance

15 16

23 24

31 32

39 40

47 48

55 56

63 64

N+2

N+3

N+4

N+1

DOUT

MSB

MODE 0

MODE 3

DOUT

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