SST26VF040A-80ISLASHSNVAO datasheet(27/73 Pages) MICROCHIP

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DS20006292B-page 27

SST26VF040A

FIGURE 5-20:

4-KBYTE SECTOR ERASE SEQUENCE (SPI)

5.18

32-Kbyte Block Erase and

64-Kbyte Block Erase

The 32-Kbyte Block Erase instruction clears all bits in

the selected 32-Kbyte block to FFH. The 64-Kbyte

Block Erase instruction clears all bits in the selected

64-Kbyte block to FFH. A 32-Kbyte Block Erase or

64-Kbyte Block Erase instruction applied to a protected

memory area will be ignored. Prior to any block erase

operation, the Write Enable (WREN) instruction must be

executed. CE# must remain active-low for the duration

of any command sequence. The 32-Kbyte Block Erase

instruction is initiated by executing an 8-bit command

52H, followed by address bits [A23:A0]. Address bits

[AMS:A15] (AMS = Most Significant Address) are used

to determine block address (BAX), remaining address

bits can be VIL or VIH. CE# must be driven high before

the instruction is executed.

The 64-Kbyte Block Erase instruction is initiated by

executing an 8-bit command D8H, followed by address

bits [A23:A0]. Address bits [AMS:A16] (AMS = Most

Significant Address) are used to determine block

address (BAX), remaining address bits can be VIL or

VIH. CE# must be driven high before the instruction is

executed. The user may poll the BUSY bit in the

software STATUS register or wait TBE for the

completion of the internal self-timed 32-Kbyte Block

Erase or 64-Kbyte Block Erase cycles. See

Figures 5-21 and 5-22 for the 32-Kbyte Block Erase

sequence and Figures 5-23 and 5-24 for the 64-Kbyte

Block Erase sequence.

FIGURE 5-21:

32-KBYTE BLOCK-ERASE SEQUENCE (SQI)

CE#

SCK

ADD.

0 1 234 5 6 78

ADD.

High-Impedance

15 16

23 24

MODE 0

MODE 3

MSB

MODE 3

SCK

SIO[3:0]

CE#

C1 C0

MODE 0

A5 A4

MSN LSN

A3 A2

A1 A0

Note:

MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = 52H

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