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ADF4212LBRU bảng dữ liệu(PDF) 9 Page - Analog Devices

tên linh kiện ADF4212LBRU
Giải thích chi tiết về linh kiện  Dual Low Power PLL Frequency Synthesizer
PDF  20 Pages
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nhà sản xuất  AD [Analog Devices]
Trang chủ  http://www.analog.com
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ADF4212LBRU bảng dữ liệu(HTML) 9 Page - Analog Devices

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REV. 0
ADF4212L
–9–
0
–20
–40
–60
–40
–20
0
20
40
TEMPERATURE – C
100
–80
–100
–120
60
80
TPC 19. RF Spurs vs. Temperature
0
–20
–40
–60
–40
–20
0
20
40
TEMPERATURE – C
100
–80
–100
–120
60
80
TPC 20. IF Spurs vs. Temperature
FREQ/
MHz
0.561872
0.529742
0.514244
0.405754
0.379354
0.312959
0.322646
0.288881
0.199294
0.206914
0.168344
0.092764
0.036125
0.037007
–0.053842
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
1450
s11.REAL
s11.IMAG
s11.REAL
s11.IMAG
–0.021077
–0.110459
–0.085802
–0.18583
–0.245482
–0.282399
–0.305457
–0.358884
–0.541032
–0.585687
–0.482539
–0.530108
–0.590526
–0.592498
–0.655932
0.97692
0.942115
0.961217
0.920667
0.897441
0.888164
0.850012
0.760189
0.767363
0.779511
0.761034
0.624825
0.635364
0.630242
0.634506
1550
1650
1750
1850
1950
2050
2150
2250
2350
2450
2550
2650
2750
2850
2950
–0.648879
–0.668172
–0.702192
–0.714541
–0.703593
–0.802878
–0.80397
–0.807055
–0.758619
–0.725029
–0.770837
–0.778619
–0.706197
–0.716939
–0.736527
FREQ/
MHz
TPC 21. S Parameter Data for the RF Input
CIRCUIT DESCRIPTION
Reference Input Section
The Reference Input Stage is shown in Figure 2. SW1 and SW2
are normally-closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
POWER-DOWN
CONTROL
REFIN NC
NC
NO
SW3
SW2
SW1
100k
BUFFER
TO R COUNTER
NC = NO CONNECT
Figure 2. Reference Input Stage
RF/IF Input Stage
The RF/IF Input Stage is shown in Figure 3. It is followed by a
two-stage limiting amplifier to generate the CML (Current Mode
Logic) clock levels needed for the prescaler.
2k
2k
1.6V
BIAS
GENERATOR
RFINA
RFINB
AVDD
AGND
Figure 3. RF/IF Input Stage



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