MCIMX6DP6AYM2AB datasheet(14/160 Pages) NXP

14 / 160 page

i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018

NXP Semiconductors

Modules List

PRE1

PRE2

PRE3

PRE4

Prefetch/Resolve

Engine

Multimedia

Peripherals

The PRE includes the Resolve engine, Prefetch engine, and Store engine

3 blocks.The PRE key features are:

The Resolve engine supports:

• GPU 32bpp 4x4 standard tile, 4x4 split tile, 4x4 super tile, 4x4 super

split tile format.

• GPU 16bpp 8x4 standard tile, 8x4 split tile, 8x4 super tile, 8x4 super

split format.

• 32/16x4 block mode and scan mode.

The prefetch engine supports:

• Transfer of non-interleaved YUV422(NI422), non-interleaved

YUV420(NI420), partial interleaved YUV422(PI422), and partial

interleaved YUV420(PI420), inputs to interleaved YUV422.

• Vertical flip function both in block mode and scan mode. In block mode,

vertical flip function should complete with TPR module enable.

• 8bpp, 16bpp, 32bpp and 64bpp data format as generic data.

• Transfer of non-interleaved YUV444(NI444), input to interleaved

YUV444 output.

The store Engine supports: 4/8/16 lines handshake modes with PRG.

PRG1

PRG2

Prefetch/Resolve

Gasket

Multimedia

Peripherals

The PRG is a digital core function which works as a gasket interface

between the fabric and the IPU system. The primary function is to re-map

the ARADDR from a frame-based address to a band-based address

depending on the different ARIDs. The PRG also implements the

handshake logic with the Prefetch Resolve Engine (PRE).

PMU

Power-Management

Functions

Data Path

Integrated power management unit. Used to provide power to various

SoC domains.

PWM-1

PWM-2

PWM-3

PWM-4

Pulse Width

Modulation

Connectivity

Peripherals

The pulse-width modulator (PWM) has a 16-bit counter and is optimized

to generate sound from stored sample audio images and it can also

generate tones. It uses 16-bit resolution and a 4x16 data FIFO to generate

sound.

RAM

16 KB

Secure/non-secure

RAM

Secured

Internal

Memory

Secure/non-secure Internal RAM, interfaced through the CAAM.

RAM

512 KB

Internal RAM

Internal

Memory

Internal RAM, which is accessed through OCRAM memory controllers.

ROM

96 KB

Boot ROM

Internal

Memory

Supports secure and regular Boot Modes. Includes read protection on 4K

region for content protection

SATA

Serial ATA

Connectivity

Peripherals

The SATA controller and PHY is a complete mixed-signal IP solution

designed to implement SATA II, 3.0 Gbps HDD connectivity.

Table 2. i.MX 6DualPlus/6QuadPlus Modules List (continued)

Block

Mnemonic

Block Name

Subsystem

Brief Description

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