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USB2641 bảng dữ liệu(PDF) 42 Page - Microchip Technology |
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USB2641 bảng dữ liệu(HTML) 42 Page - Microchip Technology |
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42 / 60 page ![]() USB2640/USB2641 DS00001947C-page 42 2015-2021 Microchip Technology Inc. 7.5.2.1 nRESET for EEPROM Configuration 7.5.3 USB BUS RESET In response to the upstream port signaling a reset to the device, the device does the following: 1. Sets default address to ‘0’. 2. Sets configuration to: Unconfigured. 3. Negates PRTCTL[3:2] to all downstream ports. 4. Clears all TT buffers. 5. Moves device from suspended to active (if suspended). 6. Complies with Section 11.10 of the USB 2.0 Specification for behavior after completion of the reset sequence. The host then configures the device and the device’s downstream port devices in accordance with the USB 2.0 Speci- fication. FIGURE 7-1: NRESET TIMING FOR EEPROM MODE TABLE 7-6: NRESET TIMING FOR EEPROM MODE Name Description MIN TYP MAX Units t1 nRESET asserted. 1 sec t2 Device recovery/stabilization. 500 sec t3 8051 programs device configuration 20 50 msec t4 USB attach (See Note). 100 msec t5 Host acknowledges attach and signals USB reset. 100 msec t6 USB idle. Undefined msec t7 Completion time for requests (with or without data stage). 5 msec Note: All power supplies must have reached the operating levels mandated in Section 9.0, "DC Parameters," on page 47, prior to (or coincident with) the assertion of nRESET. Note: The device does not propagate the upstream USB reset to downstream devices. t1 t2 t4 t5 t6 t7 nRESET VSS Hardware reset asserted Device Recovery/ Stabilization 8051 Sets Configuration Registers Attach USB Upstream USB Reset recovery Idle Start completion request response t3 |
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