ADC3641 datasheet(38/77 Pages) TI

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8.3.5 Digital Interface

The ADC364x family supports two different CMOS output modes - parallel DDR output and serialized CMOS

output formats.

8.3.5.1 Parallel CMOS Output

The low power CMOS interface supports a double data rate (DDR) output interface. In DDR output mode the

output clock is generated inside the ADC364x. The digital interface can be configured using SPI register writes.

8.3.5.2 Serialized CMOS output

In this mode the output data is serialized and transmitted over 2, 1 or 1/2 wires. Due to CMOS output speed

limitation this mode is only available for reduced output data rates. This mode is similar to the multi-SPI

interface.

In this operating mode, the ADC364x requires an external serial clock input (DCLKIN), which is used to transmit

the data out of the ADC along with the data clock (DCLK). The phase relationship between DCLKIN and the

sampling clock is irrelevant but both clocks need to be frequency locked. The serial CMOS interface is

configured using SPI register writes.

8.3.5.2.1 SDR Output Clocking

The ADC364x provides a SDR output clocking option for all serial CMOS output modes (including decimation)

which is enabled using the SPI interface. In serial CMOS mode by default the data is output on rising and falling

edge of DCLK. In SDR clocking mode, DCLKIN has to be twice as fast as the default DCLKIN so that the output

data are clocked out only on DCLK rising edge.

Internally DCLKIN is divided by 2 for data processing and this operation can add 1 extra clock cycle latency to

the ADC latency.

Continous

Clock

Sample N

Latency (2 clock cycles)

Sample N+4

DCLKIN

tAD

tPD

DCLK

Sample N+1

Sample N+2

Sample N+3

Sample N+5

Sample N+6

Sample N

DA/B5

(MSB)

DA/B6

(LSB)

FCLK

Sample N+1

Sample N+2

Sample N-1

tCD

DCLKIN

SDR

DCLK

SDR

Figure 8-38. SDR Output Clocking

ADC3643

SBAS886 – OCTOBER 2020

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