ADC3641 datasheet(35/77 Pages) TI

tên linh kiện	ADC3641

Giải thích chi tiết về linh kiện	ADC364x 14-bit, 10-MSPS to 65-MSPS, Low-Noise, Low Power Dual Channel ADC

PDF	77 Pages

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8.3.4.6 Output Formatting with Decimation

8.3.4.6.1 Parallel CMOS

In parallel CMOS mode, the ADC364x device only supports real output with DDR CMOS interface as shown in

Figure 8-35 (real decimation). Here the output format is selected to 14-bit since the parallel output bus only

supports up to 14-bit.

DCLK

DB6

(MSB)

DB0

DA6

(MSB)

DA0

DCLK

DDR CMOS

ChA/B:

DA0..DB0

D13

Figure 8-35. Output Data Format in Real Decimation

Table 8-4 illustrates the output interface data rate along with the corresponding DCLK frequency based on real

decimation setting (M).

Furthermore the table shows an actual lane rate example with complex decimation by 4.

Table 8-4. Parallel CMOS Data Rate Examples with Decimation

REAL/COMPLEX

DECIMATION

SETTING

ADC SAMPLING RATE

DDR CMOS

DCLK

DOUT

Real

DDR

FS / M

FS x 2 / M

65 MHz

DDR

16.25 MHz

32.5 MHz

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ADC3643

SBAS886 – OCTOBER 2020

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