ICS44004AI04L datasheet(9/13 Pages) ICST

9 / 13 page

844004AGI-04

www.icst.com/products/hiperclocks.html

REV. A JANUARY 26, 2006

Integrated

Circuit

Systems, Inc.

ICS844004I-04

FEMTOCLOCKS™CRYSTAL/LVCMOS-TO-

LVDS FREQUENCY SYNTHESIZER

PRELIMINARY

SCHEMATIC EXAMPLE

Figure 4 shows a schematic example for ICS844004i-04. In this

example, the input is a 19.44MHz parallel resonant crystal with

load capacitor CL=18pF. The 22pF frequency fine tuning

capacitors are used C1 and C2.This example also shows general

logic control input handling. For decoupling capacitors, it is

recommended to have one decouple capacitor per power pin.

0.1u

VCCO

0.1u

RD2

Logic Control Input Examples

Zo = 50 Ohm

RD1

Not Install

27pF

RU1

100

VCC

VCCO

0.1u

VCC

RU2

Not Install

19.44MHz

33pF

VCC

To Logic

Input

pins

844004i-04

Set Logic

Input to

'0'

VCC

0.1u

100

VCCO=3.3V

Zo = 50 Ohm

Set Logic

Input to

'1'

18pF

To Logic

Input

pins

0.01u

VCCA

10uF

VCC=3.3V

Zo = 50 Ohm

FIGURE 4. ICS844004I-04 SCHEMATIC EXAMPLE

Each decoupling capacitor should be located as close as

possible to the power pin. The low pass filter R2, C3 and C4

should also be located as close to the VCCA pin as possible.

For LVDS driver, the unused output pairs should be terminated

with a 100

Ω resistor across.

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