ICS44004AI04L datasheet(8/13 Pages) ICST

8 / 13 page

844004AGI-04

www.icst.com/products/hiperclocks.html

REV. A JANUARY 26, 2006

Integrated

Circuit

Systems, Inc.

ICS844004I-04

FEMTOCLOCKS™CRYSTAL/LVCMOS-TO-

LVDS FREQUENCY SYNTHESIZER

PRELIMINARY

3.3V LVDS DRIVER TERMINATION

A general LVDS interface is shown in Figure 3. In a 100

differential transmission line environment, LVDS drivers

require a matched load termination of 100

Ω across near

FIGURE 3. TYPICAL LVDS DRIVER TERMINATION

the receiver input. For a multiple LVDS outputs buffer, if

only partial outputs are used, it is recommended to termi-

nate the unused outputs.

100

3.3V

100 Ohm Differential Transmission Line

3.3V

LVDS

INPUTS:

CRYSTAL INPUT:

For applications not requiring the use of the crystal oscillator

input, both XTAL_IN and XTAL_OUT can be left floating.

Though not required, but for additional protection, a 1k

resistor can be tied from XTAL_IN to ground.

CLK INPUT:

For applications not requiring the use of a clock input, it can

be left floating. Though not required, but for additional

protection, a 1k

Ω resistor can be tied from the CLK input to

ground.

LVCMOS CONTROL PINS:

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1k

Ω resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

LVDS

All unused LVDS outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential

output pair should either be left floating or terminated.

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