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ICS670M-03ILF bảng dữ liệu(PDF) 5 Page - Integrated Circuit Systems |
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ICS670M-03ILF bảng dữ liệu(HTML) 5 Page - Integrated Circuit Systems |
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5 / 6 page ![]() LOW PHASE NOISE, ZERO DELAY BUFFER AND MULTIPLIER MDS 670-03 G 5 Revision 010306 Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com ICS670-03 Figure 1. Skew from ICLK to CLK2, with change in load capacitance (VDD = 3.3V) Adjusting Input/Output Skew The data in Figure 1 can be used to adjust individual circuit characteristics and achieve the minimum possible skew between ICLK and CLK2. With a 125 MHz output, for example, having a total load capacitance of 15 pF will result in nearly zero skew between ICLK and CLK2. Note that the load capacitance includes board trace capacitance, input capacitance of the load being driven by the ICS670-03, and any additional capacitors connected to CLK2. Figure 2. Phase Noise at 125 MHz out, 25 MHz clock input (VDD = 3.3V) -400 -300 -200 -100 0 100 200 300 25 50 75 100 125 150 CLK2 Frequency (MHz) Skew (ps) 20 pF Skew (ps) 10 pF ICS670 Phase noise -140 -120 -100 -80 -60 -40 -20 0 10.E+0 100.E+0 1.E+3 10.E+3 100.E+3 1.E+6 10.E+6 offset frequency |
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