83026BMI-01

www.icst.com/products/hiperclocks.html

REV. A JANUARY 16, 2006

9

Integrated

Circuit

Systems, Inc.

ICS83026I-01

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

and R2/R1 = 0.609.

V_REF

R1

1K

C1

0.1u

R2

1K

Single Ended Clock Input

CLK

nCLK

VDD

All unused LVCMOS output can be left floating. We recommend

that there is no trace attached.