83026BMI-01

www.icst.com/products/hiperclocks.html

REV. A JANUARY 16, 2006

11

Integrated

Circuit

Systems, Inc.

ICS83026I-01

Figure 3 shows an application schematic example of ICS83026I-

01. The ICS83026I-01 CLK/nCLK input can directly accepts

various types of differential signal. In this example, the input is

driven by an LVDS driver. The ICS83026I-01 outputs are

VDDO

R1

43

LVDS

VDD

R4

100

VDD=3.3V

LVCMOS

Zo = 50 Ohm

R3

1K

C2

0.1u

3.3V

Zo = 50 Ohm

VDDO= 3.3V, 2.5V or 1.8V

Zo = 50 Ohm

U1

ICS83026I-01

1

2

3

4

8

7

6

5

VDD

CLK

nCLK

OE

VDDO

Q0

Q1

GND

LVCMOS

R2

43

C1

0.1u

VDD

Zo = 50 Ohm

LVCMOS drivers. In this example, series termination approach

is shown. Additional termination approaches are shown in the

LVCMOS Termination Application Note.

The transistor count for ICS83026I-0I is: 260

θ

JA

VS

θθθθθ

0

200

500

Single-Layer PCB, JEDEC Standard Test Boards

153.3°C/W

128.5°C/W

115.5°C/W

Multi-Layer PCB, JEDEC Standard Test Boards

112.7°C/W

103.3°C/W

97.1°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

θ

JA

VS

θθθθθ

0

200

500

Multi-Layer PCB, JEDEC Standard Test Boards

101.7°C/W

90.5°C/W

89.8°C/W