AD9517-2ASLASHPCBZ datasheet(54/80 Pages) AD

tên linh kiện	AD9517-2A/PCBZ

Giải thích chi tiết về linh kiện	12-Output Clock Generator with Integrated 2.2 GHz VCO

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54 / 80 page

AD9517-2

Data Sheet

Rev. F | Page 54 of 80

SCLK DON'T CARE

DON'T CARE

16-BIT INSTRUCTION HEADER

SDIO

DON'T CARE

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12

R/W

D2 D3 D4

D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

Figure 68. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes Data

SCLK

SDIO

tHIGH

tLOW

tCLK

tDS

tDH

BIT N

BIT N + 1

Figure 69. Serial Control Port Timing—Write

Table 50. Serial Control Port Timing

Parameter

Description

tDS

Setup time between data and rising edge of SCLK

tDH

Hold time between data and rising edge of SCLK

tCLK

Period of the clock

Setup time between CS falling edge and SCLK rising edge (start of communication cycle)

Setup time between SCLK rising edge and CS rising edge (end of communication cycle)

tHIGH

Minimum period that SCLK should be in a logic high state

tLOW

Minimum period that SCLK should be in a logic low state

tDV

SCLK to valid SDIO and SDO (see Figure 67)

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