IMX6SDLCEC datasheet(128/169 Pages) NXP

128 / 169 page

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

128

NXP Semiconductors

Electrical Characteristics

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

AUDx_TXC/AUDx_RXC and/or the frame sync

AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

•

For internal Frame Sync operation using external clock, the frame sync

timing is same as that of transmit data (for example, during AC97 mode

of operation).

4.11.19.4 SSI Receiver Timing with External Clock

Figure 94 depicts the SSI receiver external clock timing and Table 85 lists the timing parameters for the

receiver timing with the external clock.

Figure 94. SSI Receiver External Clock Timing Diagram

Synchronous External Clock Operation

SS44

AUDx_RXD setup before AUDx_TXC falling

10.0

—

SS45

AUDx_RXD hold after AUDx_TXC falling

2.0

—

SS46

AUDx_RXD rise/fall time

—

6.0

Table 84. SSI Transmitter Timing with External Clock (continued)

Parameter

Min

Max

Unit

SS24

SS34

SS35

SS30

SS28

SS26

SS25

SS23

SS40

SS22

SS32

SS36

SS41

AUDx_TXC

(Input)

AUDx_TXFS (bl)

(Input)

AUDx_TXFS (wl)

(Input)

AUDx_RXD

(Input)

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