IMX6SDLCEC datasheet(91/169 Pages) NXP

91 / 169 page

Electrical Characteristics

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Figure 58. TMDS Output Signals Rise and Fall Time Definition

Table 62. Switching Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

TMDS Drivers Specifications

—

Maximum serial data rate

—

3.4

Gbps

TMDSCLK

TMDSCLK frequency

On TMDSCLKP/N outputs

—

340

MHz

TMDSCLK

TMDSCLK period

RL = 50

See Figure 54.

2.94

—

CDC

TMDSCLK duty cycle

CDC

= t

CPH

/ P

TMDSCLK

RL = 50

See Figure 54.

CPH

TMDSCLK high time

RL = 50

See Figure 54.

UI1

1 UI means TMDS clock unit.

CPL

TMDSCLK low time

RL = 50

See Figure 54.

UI1

—

TMDSCLK jitter2

2 Relative to ideal recovery clock, as specified in the HDMI specification, version 1.4a, section 4.2.3.

RL = 50

—

0.25

UI1

SK(p)

Intra-pair (pulse) skew

RL = 50

See Figure 56.

—

0.15

UI1

SK(pp)

Inter-pair skew

RL = 50

See Figure 57.

——

UI1

Differential output signal rise

time

20–80%

RL = 50

See Figure 58.

—

0.4 UI

Differential output signal fall time

20–80%

RL = 50

See Figure 58.

—

0.4 UI

—

Differential signal overshoot

Referred to 2x VSWING

——

—

Differential signal undershoot

Referred to 2x VSWING

——

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