IMX6SDLCEC datasheet(41/169 Pages) NXP

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Electrical Characteristics

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

4.6.3

DDR I/O DC Parameters

The DDR I/O pads support LPDDR2 and DDR3/DDR3L operational modes.

4.6.3.1

LPDDR2 Mode I/O DC Parameters

For details on supported DDR memory configurations, see Section 4.9.4, “Multi-Mode DDR Controller

(MMDC).

Pull-up resistor (47_k

Ω PU)

RPU_47K

Vin=OVDD

—

Pull-up resistor (100_k

Ω PU)

RPU_100K

Vin=0V

—

Pull-up resistor (100_k

Ω PU)

RPU_100K

Vin=OVDD

—

Pull-down resistor (100_k

Ω PD)

RPD_100K

Vin=OVDD

—

Pull-down resistor (100_k

Ω PD)

RPD_100K

Vin=0V

—

Input current (no PU/PD)

IIN

VI = 0, VI = OVDD

-1

Keeper Circuit Resistance

R_Keeper

VI = 0.3

× OVDD, VI = 0.7 × OVDD

105

175

1 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be

controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods.

Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

2 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.

3 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

Table 24. LPDDR2 I/O DC Electrical Parameters1

1 Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.

Parameters

Symbol

Test Conditions

Min

Max

Unit

High-level output voltage

VOH

Ioh= -0.1mA

0.9

× OVDD

—

Low-level output voltage

VOL

Iol= 0.1mA

—

0.1

× OVDD

Input Reference Voltage

Vref

—

0.49

× OVDD

0.51

× OVDD

DC High-Level input voltage

Vih_DC

—

Vref+0.13

OVDD

DC Low-Level input voltage

Vil_DC

—

OVSS

Vref-0.13

Differential Input Logic High

Vih_diff

—

0.26

Note2

2 The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as

the limitations for overshoot and undershoot.

Differential Input Logic Low

Vil_diff

—

Note3

-0.26

Pull-up/Pull-down Impedance Mismatch

Mmpupd

—

-15

240

Ω unit calibration resolution

Rres

—

Keeper Circuit Resistance

Rkeep

—

110

175

Input current (no pull-up/down)

Iin

VI = 0, VI = OVDD

-2.5

2.5

μA

Table 23. GPIO DC Parameters (continued)

Parameter

Symbol

Test Conditions

Min

Max

Units

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