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AT45DB321E bảng dữ liệu(PDF) 6 Page - Dialog Semiconductor

tên linh kiện AT45DB321E
Giải thích chi tiết về linh kiện  32-Mbit DataFlash (with Extra 1-Mbits), 2.3V Minimum SPI Serial Flash Memory
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AT45DB321E
8784L–DFLASH–3/2019
3.
Memory Array
To provide optimal flexibility, the AT45DB321E memory array is divided into three levels of granularity comprising of
sectors, blocks, and pages. Figure 3-1, Memory Architecture Diagram illustrates the breakdown of each level and details
the number of pages per sector and block. Program operations to the DataFlash can be done at the full page level or at
the byte level (a variable number of bytes). The erase operations can be performed at the chip, sector, block, or page
level.
Figure 3-1.
Memory Architecture Diagram
Sector 0a = 8 pages
4,096/4,224 bytes
Sector 0b = 120 pages
61,440/63,360 bytes
Block = 4,096/4,224 bytes
8 Pages
Sector 0a
Page = 512/528 bytes
Page 0
Page 1
Page 6
Page 7
Page 8
Page 9
Page 8,190
Page 8,191
Page 14
Page 15
Page 16
Page 17
Page 18
Sector Architecture
Block Architecture
Page Architecture
Block 0
Block 1
Block 14
Block 15
Block 16
Block 17
Block 1,022
Block 1,023
Block 30
Block 31
Block 32
Block 33
Sector 63 = 128 pages
65,536/67,584 bytes
Block 2
Sector 1 = 128 pages
65,536/67,584 bytes
Sector 62 = 128 pages
65,536/67,584 bytes
Sector 2 = 128 pages
65,536/67,584 bytes



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