AT25SF641 datasheet(37/76 Pages) DIALOG

tên linh kiện	AT25SF641

Giải thích chi tiết về linh kiện	64-Mbit, 2.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

PDF	76 Pages

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AT25SF641

DS-25SF641–111E–3/2018

Figure 7-31. 64KB Block Erase Instruction (QPI Mode)

7.20

Chip Erase (C7h / 60h)

The Chip Erase instruction clears all bits in the device to be FFh (all 1s). Prior to the Chip Erase Instruction, a Write

Enable instruction must be issued. The instruction is initiated by driving the CS pin low and shifting the instruction code

“C7h” or “60h”. (Please refer to Figure 7-32). The CS pin must go high after the eighth bit of the last byte has been

latched in, otherwise, the Chip Erase instruction will not be executed. After CS is driven high, the self-timed Chip Erase

instruction will commence for a duration of t

CE (See Section 8.7, AC Electrical Characteristics).

While the Chip Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the status

of the BUSY bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when the cycle is finished and the

device is ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch (WEL) bit in

the Status Register is cleared to 0. The Chip erase instruction is not executed if any page is protected by the Protect

(CMP, SEC, TB, BP2, BP1 and BP0) bits.

Figure 7-32. Chip Erase Instruction for SPI Mode (left) and QPI Mode (right)

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